255 lines
7.5 KiB
C
255 lines
7.5 KiB
C
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* The main header file of Samsung Exynos SMFC Driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _MEDIA_EXYNOS_SMFC_H_
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#define _MEDIA_EXYNOS_SMFC_H_
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#include <linux/ktime.h>
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#include <linux/pm_qos.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-mem2mem.h>
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#include <media/v4l2-ctrls.h>
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#include "smfc-regs.h"
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#define MODULE_NAME "exynos-jpeg"
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struct device;
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struct video_device;
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struct smfc_image_format {
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const char *description;
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__u32 v4l2_pixfmt;
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u32 regcfg;
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unsigned char bpp_buf[3];
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unsigned char bpp_pix[3];
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unsigned char num_planes;
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unsigned char num_buffers;
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unsigned char chroma_hfactor;
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unsigned char chroma_vfactor;
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};
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extern const struct smfc_image_format smfc_image_formats[];
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#define SMFC_DEFAULT_OUTPUT_FORMAT (&smfc_image_formats[1])
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#define SMFC_DEFAULT_CAPTURE_FORMAT (&smfc_image_formats[0])
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static inline bool is_jpeg(const struct smfc_image_format *fmt)
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{
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return fmt->bpp_buf[0] == 0;
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}
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/* SMFC SPECIFIC DEVICE CAPABILITIES */
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/* set if H/W supports for decompression */
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#define V4L2_CAP_EXYNOS_JPEG_DECOMPRESSION 0x0100
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/* set if H/W can compress dual images */
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#define V4L2_CAP_EXYNOS_JPEG_B2B_COMPRESSION 0x0200
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/* set if H/W supports for Hardware Flow Control */
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#define V4L2_CAP_EXYNOS_JPEG_HWFC 0x0400
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/* set if H/W supports for HWFC on internal buffers */
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#define V4L2_CAP_EXYNOS_JPEG_HWFC_EMBEDDED 0x0800
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/* set if H/W has a register to configure stream buffer size */
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#define V4L2_CAP_EXYNOS_JPEG_MAX_STREAMSIZE 0x1000
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/* set if H/W does not have 128-bit alignment constraint for stream base */
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#define V4L2_CAP_EXYNOS_JPEG_NO_STREAMBASE_ALIGN 0x2000
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/* set if H/W does not have 128-bit alignment constraint for image base */
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#define V4L2_CAP_EXYNOS_JPEG_NO_IMAGEBASE_ALIGN 0x4000
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/*
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* Set if the driver requires the address of SOS marker for the start address
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* of the JPEG stream. Unset if the driver requires the address of SOI marker
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* for the start address of the JPEG stream even though H/W requires the address
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* of SOS marker to decompress when the driver is able to find the address of
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* SOS marker from the given address of SOI marker.
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*/
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#define V4L2_CAP_EXYNOS_JPEG_DECOMPRESSION_FROM_SOS 0x10000
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/* set if H/W supports for cropping during decompression */
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#define V4L2_CAP_EXYNOS_JPEG_DECOMPRESSION_CROP 0x20000
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/* set if H/W supports for downscaling(1/2, 1/4 and 1/8) during decompression */
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#define V4L2_CAP_EXYNOS_JPEG_DOWNSCALING 0x40000
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/* set if vb2 supports offset of dmabuf */
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#define V4L2_CAP_EXYNOS_JPEG_DMABUF_OFFSET 0x80000
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struct smfc_device_data {
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__u32 device_caps;
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unsigned char burstlenth_bits;
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};
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/* Set when H/W starts, cleared in irq/timeout handler */
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#define SMFC_DEV_RUNNING (1 << 0)
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/* Set when suspend handler is called, cleared before irq handler returns. */
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#define SMFC_DEV_SUSPENDING (1 << 1)
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/* Set when timeout handler is called, cleared before the handler returns. */
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#define SMFC_DEV_TIMEDOUT (1 << 3)
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/* Set if HWFC is enabled in device_run, cleared in irq/timeout handler */
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#define SMFC_DEV_OTF_EMUMODE (1 << 4)
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struct smfc_dev {
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struct v4l2_device v4l2_dev;
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struct video_device *videodev;
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struct v4l2_m2m_dev *m2mdev;
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struct device *dev;
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void __iomem *reg;
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const struct smfc_device_data *devdata;
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spinlock_t flag_lock;
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struct mutex video_device_mutex;
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struct timer_list timer;
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int device_id;
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u32 hwver;
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u32 flags;
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struct clk *clk_gate;
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struct clk *clk_gate2; /* available if clk_gate is valid */
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struct pm_qos_request qosreq_int;
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s32 qosreq_int_level;
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};
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#define SMFC_CTX_COMPRESS (1 << 0)
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#define SMFC_CTX_B2B_COMPRESS (1 << 1) /* valid if SMFC_CTX_COMPRESS is set */
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static inline bool smfc_is_capable(const struct smfc_dev *smfc, u32 capability)
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{
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return (smfc->devdata->device_caps & capability) == capability;
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}
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struct smfc_decomp_htable {
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struct {
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union {
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u8 code[SMFC_NUM_HCODE];
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u32 code32[SMFC_NUM_HCODE / 4];
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};
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union {
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u8 value[SMFC_NUM_DC_HVAL];
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u32 value32[SMFC_NUM_DC_HVAL / 4];
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};
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} dc[2];
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struct {
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union {
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u8 code[SMFC_NUM_HCODE];
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u32 code32[SMFC_NUM_HCODE / 4];
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};
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union {
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u8 value[SMFC_NUM_AC_HVAL];
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u32 value32[SMFC_NUM_AC_HVAL / 4];
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};
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} ac[2];
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struct {
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unsigned char idx_dc;
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unsigned char idx_ac;
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} compsel[SMFC_MAX_NUM_COMP]; /* compsel[0] for component 1 */
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};
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#define INVALID_QTBLIDX 0xFF
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struct smfc_decomp_qtable {
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/* quantizers are *NOT* stored in the zig-zag scan order */
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u8 table[SMFC_MAX_QTBL_COUNT][SMFC_MCU_SIZE];
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char compsel[SMFC_MAX_QTBL_COUNT];
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};
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struct smfc_crop {
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u32 width;
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u32 height;
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u32 po[SMFC_MAX_NUM_COMP];
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u32 so[SMFC_MAX_NUM_COMP];
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};
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struct smfc_ctx {
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struct v4l2_fh fh;
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struct v4l2_ctrl_handler v4l2_ctrlhdlr;
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struct smfc_dev *smfc;
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ktime_t ktime_beg;
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u32 flags;
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/* uncomressed image description */
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const struct smfc_image_format *img_fmt;
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__u32 width;
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__u32 height;
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/* cropping size settings */
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struct smfc_crop crop;
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/* Compression settings */
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unsigned char chroma_hfactor; /* horizontal chroma subsampling factor */
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unsigned char chroma_vfactor; /* vertical chroma subsampling factor */
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unsigned char restart_interval;
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unsigned char quality_factor;
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struct v4l2_ctrl *ctrl_qtbl2;
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/*
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* thumbnail information:
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* format of thumbnail should be the same as the main image
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* It is not the H/W restriction. Just a choice for simpler S/W design.
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*/
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__u32 thumb_width;
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__u32 thumb_height;
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unsigned char thumb_quality_factor;
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unsigned char enable_hwfc;
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/* Decompression settings */
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struct smfc_decomp_qtable *quantizer_tables;
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struct smfc_decomp_htable *huffman_tables;
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unsigned char stream_hfactor;
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unsigned char stream_vfactor;
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unsigned char num_components;
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unsigned int offset_of_sos;
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__u16 stream_width;
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__u16 stream_height;
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};
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extern const struct v4l2_ioctl_ops smfc_v4l2_ioctl_ops;
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static inline struct smfc_ctx *v4l2_fh_to_smfc_ctx(struct v4l2_fh *fh)
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{
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return container_of(fh, struct smfc_ctx, fh);
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}
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/* return the previous flag */
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static inline u32 smfc_config_ctxflag(struct smfc_ctx *ctx, u32 flag, bool set)
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{
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u32 prevflags = ctx->flags;
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ctx->flags = set ? ctx->flags | flag : ctx->flags & ~flag;
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return prevflags;
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}
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static inline bool smfc_is_compressed_type(struct smfc_ctx *ctx, __u32 type)
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{
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return (!(ctx->flags & SMFC_CTX_COMPRESS)) == V4L2_TYPE_IS_OUTPUT(type);
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}
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int smfc_init_controls(struct smfc_dev *smfc, struct v4l2_ctrl_handler *hdlr);
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int smfc_parse_jpeg_header(struct smfc_ctx *ctx, struct vb2_buffer *vb);
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/* H/W Configuration */
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void smfc_hwconfigure_tables(struct smfc_ctx *ctx,
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unsigned int qfactor, const u8 qtbl[]);
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void smfc_hwconfigure_tables_for_decompression(struct smfc_ctx *ctx);
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void smfc_hwconfigure_image(struct smfc_ctx *ctx,
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unsigned int hfactor, unsigned int vfactor);
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void smfc_hwconfigure_start(struct smfc_ctx *ctx,
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unsigned int rst_int, bool hwfc_en);
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void smfc_hwconfigure_2nd_tables(struct smfc_ctx *ctx, unsigned int qfactor);
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void smfc_hwconfigure_2nd_image(struct smfc_ctx *ctx, bool hwfc_enabled);
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bool smfc_hwstatus_okay(struct smfc_dev *smfc, struct smfc_ctx *ctx);
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void smfc_hwconfigure_reset(struct smfc_dev *smfc);
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void smfc_dump_registers(struct smfc_dev *smfc);
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static inline u32 smfc_get_streamsize(struct smfc_dev *smfc)
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{
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return __raw_readl(smfc->reg + REG_MAIN_STREAM_SIZE);
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}
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static inline u32 smfc_get_2nd_streamsize(struct smfc_dev *smfc)
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{
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return __raw_readl(smfc->reg + REG_SEC_STREAM_SIZE);
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}
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#endif /* _MEDIA_EXYNOS_SMFC_H_ */
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