186 lines
6.4 KiB
C
186 lines
6.4 KiB
C
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* The SFR definition file of Samsung Exynos SMFC Driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _MEDIA_EXYNOS_SMFC_REGS_H_
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#define _MEDIA_EXYNOS_SMFC_REGS_H_
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/********** JPEG STANDARD *****************************************************/
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#define SMFC_JPEG_MARKER_LEN 2
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#define SMFC_MCU_SIZE 64
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#define SMFC_MAX_QTBL_COUNT 4
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#define SMFC_NUM_HCODE 16
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#define SMFC_NUM_DC_HVAL 16
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#define SMFC_NUM_AC_HVAL 172
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/********** H/W RESTRICTIONS **************************************************/
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#define SMFC_MAX_NUM_COMP 3
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#define SMFC_MAX_WIDTH 16368U
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#define SMFC_MAX_HEIGHT 16368U
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#define SMFC_MIN_WIDTH 8U
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#define SMFC_MIN_HEIGHT 8U
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#define SMFC_ADDR_ALIGN_MASK(burstlen) ((burstlen) - 1)
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#define SMFC_STREAMSIZE_ALIGN 64
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#define SMFC_STREAMSIZE_ALIGN_MASK (64 - 1)
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#define SMFC_EXTRA_STREAMSIZE(base, burstlen) \
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(SMFC_STREAMSIZE_ALIGN - ((base) & SMFC_ADDR_ALIGN_MASK(burstlen)))
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/********** H/W REGISTERS and DEFAULT VALUES **********************************/
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#define REG_MAIN_JPEG_CNTL 0x000
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# define JPEG_CNTL_CODECON_MASK 3
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# define JPEG_CNTL_CODECON_COMPRESS 2
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# define JPEG_CNTL_CODECON_DECOMPRESS 1
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# define JPEG_CNTL_INT_EN_SHIFT 28
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# define JPEG_CNTL_HWFC_EN_SHIFT 30
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# define JPEG_CNTL_BTB_EN_SHIFT 31
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# define JPEG_CNTL_RESET_MASK \
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((1 <<JPEG_CNTL_HWFC_EN_SHIFT) | (1 << JPEG_CNTL_BTB_EN_SHIFT) | \
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JPEG_CNTL_CODECON_MASK)
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#define REG_INT_EN 0x004
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#define REG_TIMER_COUNT 0x008
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#define REG_MAIN_INT_STATUS 0x00C
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#define REG_MAIN_IMAGE_SIZE 0x014
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#define REG_MAIN_JPEG_BASE 0x010
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#define REG_MAIN_IMAGE_BASE 0x018
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#define REG_MAIN_IMAGE_SO_PLANE1 0x01C
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#define REG_MAIN_IMAGE_PO_PLANE1 0x020
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#define REG_MAIN_IMAGE_SO_PLANE(n) (REG_MAIN_IMAGE_SO_PLANE1 + (n) * 12)
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#define REG_MAIN_IMAGE_PO_PLANE(n) (REG_MAIN_IMAGE_PO_PLANE1 + (n) * 12)
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#define REG_SEC_JPEG_CNTL 0x080
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#define REG_SEC_JPEG_BASE 0x088
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#define REG_SEC_IMAGE_BASE 0x090
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#define REG_SEC_IMAGE_FORMAT 0x0B8
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#define REG_SEC_IMAGE_SIZE 0x08C
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#define REG_SEC_INT_STATUS 0x084
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#define REG_IMAGE_BASE(off, n) ((off) + (n) * 12)
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#define REG_MAIN_IMAGE_FORMAT 0x040
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#define REG_MAIN_STREAM_SIZE 0x044
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#define REG_SEC_STREAM_SIZE 0x0BC
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#define REG_IP_VERSION_NUMBER 0x064
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#define REG_MAIN_TABLE_SELECT 0x03C
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#define REG_SEC_TABLE_SELECT 0x0B4
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/*
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* Component 0: Q-table 0, AC/DC table 0
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* Component 1 and 2: Q-table 1, AC/DC table 1
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*/
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#define VAL_MAIN_TABLE_SELECT 0xF14
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/*
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* Component 0: Q-table 2, AC/DC table 0
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* Component 1 and 2: Q-table 3, AC/DC table 1
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*/
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#define VAL_SEC_TABLE_SELECT 0xF3E
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#define SMFC_TABLE_READ_REQ_MASK (1 << 13)
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#define SMFC_TABLE_READ_OK_MASK (1 << 12)
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/* 64 reigsters for four quantization tables are prepared */
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#define REG_QTBL_BASE 0x100
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/*
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* Total 112 registers for huffman tables:
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* 0x200 - 4 DC Luma code lengths registers
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* 0x210 - 4 DC Luma values registers
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* 0x220 - 4 DC Chroma code lengths registers
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* 0x230 - 4 DC Chroma values registers
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* 0x240 - 4 AC Luma code lengths registers
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* 0x250 - 44 AC Luma values registers
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* 0x300 - 4 AC Chroma code lengths registers
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* 0x310 - 44 ACChroma values registers
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*/
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#define REG_HTBL_BASE 0x200
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# define REG_HTBL_LUMA_DCLEN REG_HTBL_BASE
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# define REG_HTBL_LUMA_DCVAL (REG_HTBL_LUMA_DCLEN + 4 * sizeof(u32))
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# define REG_HTBL_CHROMA_DCLEN (REG_HTBL_LUMA_DCVAL + 4 * sizeof(u32))
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# define REG_HTBL_CHROMA_DCVAL (REG_HTBL_CHROMA_DCLEN + 4 * sizeof(u32))
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# define REG_HTBL_LUMA_ACLEN (REG_HTBL_CHROMA_DCVAL + 4 * sizeof(u32))
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# define REG_HTBL_LUMA_ACVAL (REG_HTBL_LUMA_ACLEN + 4 * sizeof(u32))
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# define REG_HTBL_CHROMA_ACLEN (REG_HTBL_LUMA_ACVAL + 44 * sizeof(u32))
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# define REG_HTBL_CHROMA_ACVAL (REG_HTBL_CHROMA_ACLEN + 4 * sizeof(u32))
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#define REG_MAIN_DHT_LEN 0x04C
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#define REG_SEC_DHT_LEN 0x0C4
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#define SMFC_DHT_LEN 0x1A2
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/* Value definitions of MAIN/SECONDARY_IMAGE_FORMAT */
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enum {
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IMGSEL_GRAY,
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IMGSEL_RGB,
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IMGSEL_444, /* YUV */
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IMGSEL_422, /* YUV */
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IMGSEL_420, /* YUV */
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IMGSEL_422V, /* YUV */
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IMGSEL_411 /* YUV */
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};
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#define IMGFMT_RGBSHIFT 6
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enum {
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RGBSEL_RGB565 = 4,
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RGBSEL_ARGB32,
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RGBSEL_RGB24,
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};
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#define IMGFMT_444SHIFT 9
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#define IMGFMT_422SHIFT 12
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#define IMGFMT_420SHIFT 15
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#define IMGFMT_422VSHIFT 18
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#define IMGFMT_411SHIFT 21
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enum {
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YUVSEL_2P = 4,
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YUVSEL_3P = 5,
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YUV422SEL_1P = 4,
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YUV422SEL_2P = 5,
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YUV422SEL_3P = 6,
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};
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#define IMGFMT_RGBSWAP (1 << 30)
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#define IMGFMT_UVSWAP (1 << 27)
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enum {
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YUVSEL_YUYV = 0,
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YUVSEL_YVYU = 1 << 28,
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YUVSEL_UYVY = 2 << 28,
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YUVSEL_VYUY = 3 << 28,
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};
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#define SMFC_IMGFMT_RGB565 (IMGSEL_RGB | (RGBSEL_RGB565 << IMGFMT_RGBSHIFT))
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#define SMFC_IMGFMT_BGR565 (IMGSEL_RGB | (RGBSEL_RGB565 << IMGFMT_RGBSHIFT)\
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| IMGFMT_RGBSWAP)
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#define SMFC_IMGFMT_RGB24 (IMGSEL_RGB | (RGBSEL_RGB24 << IMGFMT_RGBSHIFT))
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#define SMFC_IMGFMT_BGR24 (IMGSEL_RGB | (RGBSEL_RGB24 << IMGFMT_RGBSHIFT) \
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| IMGFMT_RGBSWAP)
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#define SMFC_IMGFMT_BGRA32 (IMGSEL_RGB | (RGBSEL_ARGB32 << IMGFMT_RGBSHIFT))
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#define SMFC_IMGFMT_RGBA32 (IMGSEL_RGB | (RGBSEL_ARGB32 << IMGFMT_RGBSHIFT)\
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| IMGFMT_RGBSWAP)
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#define SMFC_IMGFMT_NV12 (IMGSEL_420 | (YUVSEL_2P << IMGFMT_420SHIFT))
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#define SMFC_IMGFMT_NV21 (IMGSEL_420 | (YUVSEL_2P << IMGFMT_420SHIFT) \
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| IMGFMT_UVSWAP)
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#define SMFC_IMGFMT_YUV420P (IMGSEL_420 | (YUVSEL_3P << IMGFMT_420SHIFT))
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#define SMFC_IMGFMT_YVU420P (IMGSEL_420 | (YUVSEL_3P << IMGFMT_420SHIFT) \
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| IMGFMT_UVSWAP)
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#define SMFC_IMGFMT_YUYV (IMGSEL_422 | (YUV422SEL_1P << IMGFMT_422SHIFT) \
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| YUVSEL_YUYV)
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#define SMFC_IMGFMT_YVYU (IMGSEL_422 | (YUV422SEL_1P << IMGFMT_422SHIFT) \
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| YUVSEL_YVYU)
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#define SMFC_IMGFMT_UYVY (IMGSEL_422 | (YUV422SEL_1P << IMGFMT_422SHIFT) \
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| YUVSEL_UYVY)
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#define SMFC_IMGFMT_VYUY (IMGSEL_422 | (YUV422SEL_1P << IMGFMT_422SHIFT) \
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| YUVSEL_VYUY)
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#define SMFC_IMGFMT_NV16 (IMGSEL_422 | (YUV422SEL_2P << IMGFMT_422SHIFT))
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#define SMFC_IMGFMT_NV61 (IMGSEL_422 | (YUV422SEL_2P << IMGFMT_422SHIFT) \
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| IMGFMT_UVSWAP)
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#define SMFC_IMGFMT_YUV422 (IMGSEL_422 | (YUV422SEL_3P << IMGFMT_422SHIFT))
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#define SMFC_IMGFMT_YUV444 (IMGSEL_444 | (YUVSEL_3P << IMGFMT_444SHIFT))
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#define SMFC_IMGFMT_JPEG444 (1 << 24)
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#define SMFC_IMGFMT_JPEG422 (2 << 24)
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#define SMFC_IMGFMT_JPEG420 (3 << 24)
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#define SMFC_IMGFMT_JPEG422V (4 << 24)
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#define SMFC_IMGFMT_JPEG411 (5 << 24)
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#endif /* _MEDIA_EXYNOS_SMFC_REGS_H_ */
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