377 lines
11 KiB
C
377 lines
11 KiB
C
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/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Register header file for Exynos Scaler driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SCALER_REGS_H__
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#define __SCALER_REGS_H__
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#include "scaler.h"
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/* Status */
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#define SCALER_STATUS 0x00
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/* Configuration */
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#define SCALER_CFG 0x04
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#define SCALER_CFG_DRCG_EN (1 << 31)
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#define SCALER_CFG_CORE_BYP_EN (1 << 29)
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#define SCALER_CFG_SRAM_CG_EN (1 << 28)
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#define SCALER_CFG_FILL_EN (1 << 24)
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#define SCALER_CFG_BL_DIV_ALPHA_EN (1 << 17)
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#define SCALER_CFG_BLEND_EN (1 << 16)
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#define SCALER_CFG_CSC_Y_OFFSET_SRC (1 << 10)
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#define SCALER_CFG_BURST_WR (1 << 8)
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#define SCALER_CFG_BURST_RD (1 << 7)
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#define SCALER_CFG_CSC_Y_OFFSET_DST (1 << 9)
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#define SCALER_CFG_STOP_REQ (1 << 3)
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#define SCALER_CFG_RESET_OKAY (1 << 2)
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#define SCALER_CFG_SOFT_RST (1 << 1)
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#define SCALER_CFG_START_CMD (1 << 0)
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/* Interrupt */
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#define SCALER_INT_EN 0x08
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#define SCALER_INT_EN_FRAME_END (1 << 0)
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#define SCALER_INT_EN_ALL 0x807fffff
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#define SCALER_INT_EN_ALL_v3 0x82ffffff
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#define SCALER_INT_EN_ALL_v4 0xb2ffffff
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#define SCALER_INT_OK(status) ((status) == SCALER_INT_EN_FRAME_END)
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#define SCALER_INT_STATUS 0x0c
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#define SCALER_INT_STATUS_FRAME_END (1 << 0)
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#define SCALER_SRC_CFG 0x10
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/* Source Image Configuration */
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#define SCALER_CFG_TILE_EN (1 << 10)
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#define SCALER_CFG_VHALF_PHASE_EN (1 << 9)
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#define SCALER_CFG_BIG_ENDIAN (1 << 8)
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#define SCALER_CFG_10BIT_P010 (1 << 7)
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#define SCALER_CFG_10BIT_S10 (2 << 7)
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#define SCALER_CFG_SWAP_MASK (3 << 5)
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#define SCALER_CFG_BYTE_SWAP (1 << 5)
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#define SCALER_CFG_HWORD_SWAP (2 << 5)
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#define SCALER_CFG_BYTE_HWORD_SWAP (3 << 5)
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#define SCALER_CFG_FMT_MASK (0x1f << 0)
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#define SCALER_CFG_FMT_YCBCR420_2P (0 << 0)
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#define SCALER_CFG_FMT_YUYV (0xa << 0)
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#define SCALER_CFG_FMT_UYVY (0xb << 0)
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#define SCALER_CFG_FMT_YVYU (9 << 0)
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#define SCALER_CFG_FMT_YCBCR422_2P (2 << 0)
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#define SCALER_CFG_FMT_YCBCR444_2P (3 << 0)
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#define SCALER_CFG_FMT_RGB565 (4 << 0)
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#define SCALER_CFG_FMT_ARGB1555 (5 << 0)
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#define SCALER_CFG_FMT_ARGB4444 (0xc << 0)
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#define SCALER_CFG_FMT_ARGB8888 (6 << 0)
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#define SCALER_CFG_FMT_RGBA8888 (0xe << 0)
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#define SCALER_CFG_FMT_P_ARGB8888 (7 << 0)
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#define SCALER_CFG_FMT_L8A8 (0xd << 0)
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#define SCALER_CFG_FMT_L8 (0xf << 0)
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#define SCALER_CFG_FMT_YCRCB420_2P (0x10 << 0)
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#define SCALER_CFG_FMT_YCRCB422_2P (0x12 << 0)
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#define SCALER_CFG_FMT_YCRCB444_2P (0x13 << 0)
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#define SCALER_CFG_FMT_YCBCR420_3P (0x14 << 0)
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#define SCALER_CFG_FMT_YCBCR422_3P (0x16 << 0)
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#define SCALER_CFG_FMT_YCBCR444_3P (0x17 << 0)
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/* Source Y Base Address */
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#define SCALER_SRC_Y_BASE 0x14
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#define SCALER_SRC_CB_BASE 0x18
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#define SCALER_SRC_CR_BASE 0x294
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#define SCALER_SRC_SPAN 0x1c
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#define SCALER_SRC_CSPAN_MASK (0xffff << 16)
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#define SCALER_SRC_YSPAN_MASK (0xffff << 0)
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#define SCALER_SRC_Y_POS 0x20
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#define SCALER_SRC_WH 0x24
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#define SCALER_SRC_PRESC_WH 0x2C
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#define SCALER_SRC_C_POS 0x28
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#define SCALER_DST_CFG 0x30
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#define SCALER_DST_Y_BASE 0x34
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#define SCALER_DST_CB_BASE 0x38
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#define SCALER_DST_CR_BASE 0x298
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#define SCALER_DST_SPAN 0x3c
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#define SCALER_DST_CSPAN_MASK (0xffff << 16)
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#define SCALER_DST_YSPAN_MASK (0xffff << 0)
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#define SCALER_DST_WH 0x40
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#define SCALER_DST_POS 0x44
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#define SCALER_H_RATIO 0x50
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#define SCALER_V_RATIO 0x54
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#define SCALER_ROT_CFG 0x58
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#define SCALER_ROT_MASK (3 << 0)
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#define SCALER_FLIP_MASK (3 << 2)
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#define SCALER_FLIP_X_EN (1 << 3)
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#define SCALER_FLIP_Y_EN (1 << 2)
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#define SCALER_ROT_90 (1 << 0)
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#define SCALER_ROT_180 (2 << 0)
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#define SCALER_ROT_270 (3 << 0)
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#define SCALER_LAT_CON 0x5c
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#define SCALER_YHCOEF 0x60
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#define SCALER_YVCOEF 0xf0
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#define SCALER_CHCOEF 0x140
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#define SCALER_CVCOEF 0x1d0
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#define SCALER_CSC_COEF00 0x220
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#define SCALER_CSC_COEF10 0x224
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#define SCALER_CSC_COEF20 0x228
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#define SCALER_CSC_COEF01 0x22c
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#define SCALER_CSC_COEF11 0x230
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#define SCALER_CSC_COEF21 0x234
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#define SCALER_CSC_COEF02 0x238
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#define SCALER_CSC_COEF12 0x23c
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#define SCALER_CSC_COEF22 0x240
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#define SCALER_CSC_COEF_MASK (0xffff << 0)
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#define SCALER_DITH_CFG 0x250
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#define SCALER_DITH_R_MASK (7 << 6)
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#define SCALER_DITH_G_MASK (7 << 3)
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#define SCALER_DITH_B_MASK (7 << 0)
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#define SCALER_DITH_R_SHIFT (6)
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#define SCALER_DITH_G_SHIFT (3)
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#define SCALER_DITH_B_SHIFT (0)
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#define SCALER_DITH_SRC_INV (1 << 1)
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#define SCALER_DITH_DST_EN (1 << 0)
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#define SCALER_VER 0x260
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#define SCALER_CRC_COLOR01 0x270
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#define SCALER_CRC_COLOR23 0x274
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#define SCALER_CYCLE_COUNT 0x278
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#define SCALER_SRC_BLEND_COLOR 0x280
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#define SCALER_SRC_BLEND_ALPHA 0x284
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#define SCALER_DST_BLEND_COLOR 0x288
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#define SCALER_DST_BLEND_ALPHA 0x28c
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#define SCALER_SEL_INV_MASK (1 << 31)
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#define SCALER_SEL_MASK (2 << 29)
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#define SCALER_OP_SEL_INV_MASK (1 << 28)
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#define SCALER_OP_SEL_MASK (0xf << 24)
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#define SCALER_SEL_INV_SHIFT (31)
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#define SCALER_SEL_SHIFT (29)
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#define SCALER_OP_SEL_INV_SHIFT (28)
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#define SCALER_OP_SEL_SHIFT (24)
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#define SCALER_SRC_2BIT_Y_BASE 0x280
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#define SCALER_SRC_2BIT_C_BASE 0x284
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#define SCALER_SRC_2BIT_SPAN 0x288
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#define SCALER_SRC_2BIT_YSPAN_MASK (0x7fff << 0)
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#define SCALER_SRC_2BIT_CSPAN_MASK (0x7fff << 16)
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#define SCALER_DST_2BIT_Y_BASE 0x2A0
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#define SCALER_DST_2BIT_C_BASE 0x2A4
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#define SCALER_DST_2BIT_SPAN 0x2A8
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#define SCALER_DST_2BIT_YSPAN_MASK (0x7fff << 0)
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#define SCALER_DST_2BIT_CSPAN_MASK (0x7fff << 16)
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#define SCALER_FILL_COLOR 0x290
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#define SCALER_TIMEOUT_CTRL 0x2c0
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#define SCALER_TIMEOUT_CNT 0x2c4
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#define SCALER_CLK_REQ 0x2cc
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#define SCALER_SRC_YH_INIT_PHASE 0x2d0
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#define SCALER_SRC_YV_INIT_PHASE 0x2d4
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#define SCALER_SRC_CH_INIT_PHASE 0x2d8
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#define SCALER_SRC_CV_INIT_PHASE 0x2dc
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/* macros to make words to SFR */
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#define SCALER_VAL_WH(w, h) (((w) & 0x3FFF) << 16) | ((h) & 0x3FFF)
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#define SCALER_VAL_SRC_POS(l, t) (((l) & 0x3FFF) << 18) | (((t) & 0x3FFF) << 2)
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#define SCALER_VAL_DST_POS(l, t) (((l) & 0x3FFF) << 16) | ((t) & 0x3FFF)
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static inline void sc_hwset_clk_request(struct sc_dev *sc, bool enable)
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{
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if (sc->version >= SCALER_VERSION(5, 0, 1))
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__raw_writel(enable ? 1 : 0, sc->regs + SCALER_CLK_REQ);
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}
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static inline void sc_hwset_src_pos(struct sc_dev *sc, __s32 left, __s32 top,
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unsigned int chshift, unsigned int cvshift)
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{
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/* SRC pos have fractional part of 2 bits which is not used */
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__raw_writel(SCALER_VAL_SRC_POS(left, top),
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sc->regs + SCALER_SRC_Y_POS);
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__raw_writel(SCALER_VAL_SRC_POS(left >> chshift, top >> cvshift),
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sc->regs + SCALER_SRC_C_POS);
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}
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static inline void sc_hwset_src_wh(struct sc_dev *sc, __s32 width, __s32 height,
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unsigned int pre_h_ratio, unsigned int pre_v_ratio,
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unsigned int chshift, unsigned int cvshift)
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{
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__s32 pre_width = round_down(width >> pre_h_ratio, 1 << chshift);
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__s32 pre_height = round_down(height >> pre_v_ratio, 1 << cvshift);
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sc_dbg("width %d, height %d\n", pre_width, pre_height);
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if (sc->variant->prescale) {
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/*
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* crops the width and height if the pre-scaling result violates
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* the width/height constraints:
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* - result width or height is not a natural number
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* - result width or height violates the constrains
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* of YUV420/422
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*/
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width = pre_width << pre_h_ratio;
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height = pre_height << pre_v_ratio;
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__raw_writel(SCALER_VAL_WH(width, height),
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sc->regs + SCALER_SRC_PRESC_WH);
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}
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__raw_writel(SCALER_VAL_WH(pre_width, pre_height),
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sc->regs + SCALER_SRC_WH);
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}
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static inline void sc_hwset_dst_pos(struct sc_dev *sc, __s32 left, __s32 top)
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{
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__raw_writel(SCALER_VAL_DST_POS(left, top), sc->regs + SCALER_DST_POS);
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}
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static inline void sc_hwset_dst_wh(struct sc_dev *sc, __s32 width, __s32 height)
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{
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__raw_writel(SCALER_VAL_WH(width, height), sc->regs + SCALER_DST_WH);
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}
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static inline void sc_hwset_hratio(struct sc_dev *sc, u32 ratio, u32 pre_ratio)
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{
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__raw_writel((pre_ratio << 28) | ratio, sc->regs + SCALER_H_RATIO);
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}
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static inline void sc_hwset_vratio(struct sc_dev *sc, u32 ratio, u32 pre_ratio)
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{
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__raw_writel((pre_ratio << 28) | ratio, sc->regs + SCALER_V_RATIO);
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}
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static inline void sc_hwset_flip_rotation(struct sc_dev *sc, u32 flip_rot_cfg)
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{
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__raw_writel(flip_rot_cfg & 0xF, sc->regs + SCALER_ROT_CFG);
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}
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static inline void sc_hwset_int_en(struct sc_dev *sc)
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{
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unsigned int val;
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if (sc->version < SCALER_VERSION(3, 0, 0))
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val = SCALER_INT_EN_ALL;
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else if (sc->version < SCALER_VERSION(4, 0, 1) ||
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sc->version == SCALER_VERSION(4, 2, 0))
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val = SCALER_INT_EN_ALL_v3;
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else
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val = SCALER_INT_EN_ALL_v4;
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__raw_writel(val, sc->regs + SCALER_INT_EN);
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}
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static inline void sc_clear_aux_power_cfg(struct sc_dev *sc)
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{
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/* Clearing all power saving features */
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__raw_writel(__raw_readl(sc->regs + SCALER_CFG) & ~SCALER_CFG_DRCG_EN,
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sc->regs + SCALER_CFG);
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}
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static inline void sc_hwset_bus_idle(struct sc_dev *sc)
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{
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if (sc->version == SCALER_VERSION(5, 0, 1)) {
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int cnt = 1000;
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__raw_writel(SCALER_CFG_STOP_REQ, sc->regs + SCALER_CFG);
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while (cnt-- > 0)
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if (__raw_readl(sc->regs + SCALER_CFG)
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& SCALER_CFG_RESET_OKAY)
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break;
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WARN_ON(cnt <= 0);
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}
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}
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static inline void sc_hwset_init(struct sc_dev *sc)
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{
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unsigned long cfg;
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sc_hwset_bus_idle(sc);
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#ifdef SC_NO_SOFTRST
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cfg = (SCALER_CFG_CSC_Y_OFFSET_SRC | SCALER_CFG_CSC_Y_OFFSET_DST);
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#else
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cfg = SCALER_CFG_SOFT_RST;
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#endif
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writel(cfg, sc->regs + SCALER_CFG);
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|
|
if (sc->version >= SCALER_VERSION(3, 0, 1))
|
||
|
|
__raw_writel(
|
||
|
|
__raw_readl(sc->regs + SCALER_CFG) | SCALER_CFG_DRCG_EN,
|
||
|
|
sc->regs + SCALER_CFG);
|
||
|
|
if (sc->version >= SCALER_VERSION(4, 0, 1) &&
|
||
|
|
sc->version != SCALER_VERSION(4, 2, 0)) {
|
||
|
|
__raw_writel(
|
||
|
|
__raw_readl(sc->regs + SCALER_CFG) | SCALER_CFG_BURST_RD,
|
||
|
|
sc->regs + SCALER_CFG);
|
||
|
|
__raw_writel(
|
||
|
|
__raw_readl(sc->regs + SCALER_CFG) & ~SCALER_CFG_BURST_WR,
|
||
|
|
sc->regs + SCALER_CFG);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void sc_hwset_soft_reset(struct sc_dev *sc)
|
||
|
|
{
|
||
|
|
sc_hwset_bus_idle(sc);
|
||
|
|
writel(SCALER_CFG_SOFT_RST, sc->regs + SCALER_CFG);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void sc_hwset_start(struct sc_dev *sc)
|
||
|
|
{
|
||
|
|
unsigned long cfg = __raw_readl(sc->regs + SCALER_CFG);
|
||
|
|
|
||
|
|
cfg |= SCALER_CFG_START_CMD;
|
||
|
|
if (sc->version >= SCALER_VERSION(3, 0, 1)) {
|
||
|
|
cfg |= SCALER_CFG_CORE_BYP_EN;
|
||
|
|
cfg |= SCALER_CFG_SRAM_CG_EN;
|
||
|
|
}
|
||
|
|
writel(cfg, sc->regs + SCALER_CFG);
|
||
|
|
}
|
||
|
|
|
||
|
|
u32 sc_hwget_and_clear_irq_status(struct sc_dev *sc);
|
||
|
|
|
||
|
|
#define SCALER_FRACT_VAL(x) (x << (20 - SC_CROP_FRACT_MULTI))
|
||
|
|
#define SCALER_INIT_PHASE_VAL(i, f) (((i) & 0xf << 20) | \
|
||
|
|
((SCALER_FRACT_VAL(f)) & 0xfffff))
|
||
|
|
static inline void sc_hwset_src_init_phase(struct sc_dev *sc, struct sc_init_phase *ip)
|
||
|
|
{
|
||
|
|
if (ip->yh) {
|
||
|
|
__raw_writel(SCALER_INIT_PHASE_VAL(0, ip->yh),
|
||
|
|
sc->regs + SCALER_SRC_YH_INIT_PHASE);
|
||
|
|
__raw_writel(SCALER_INIT_PHASE_VAL(0, ip->ch),
|
||
|
|
sc->regs + SCALER_SRC_CH_INIT_PHASE);
|
||
|
|
sc_dbg("initial phase value is yh 0x%x, ch 0x%x\n",
|
||
|
|
SCALER_FRACT_VAL(ip->yh), SCALER_FRACT_VAL(ip->ch));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ip->yv) {
|
||
|
|
__raw_writel(SCALER_INIT_PHASE_VAL(0, ip->yv),
|
||
|
|
sc->regs + SCALER_SRC_YV_INIT_PHASE);
|
||
|
|
__raw_writel(SCALER_INIT_PHASE_VAL(0, ip->cv),
|
||
|
|
sc->regs + SCALER_SRC_CV_INIT_PHASE);
|
||
|
|
sc_dbg("initial phase value is yv 0x%x, cv 0x%x\n",
|
||
|
|
SCALER_FRACT_VAL(ip->yv), SCALER_FRACT_VAL(ip->cv));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void sc_hwset_polyphase_hcoef(struct sc_dev *sc,
|
||
|
|
unsigned int yratio, unsigned int cratio, unsigned int filter);
|
||
|
|
void sc_hwset_polyphase_vcoef(struct sc_dev *sc,
|
||
|
|
unsigned int yratio, unsigned int cratio, unsigned int filter);
|
||
|
|
|
||
|
|
#endif /*__SCALER_REGS_H__*/
|