403 lines
10 KiB
C
403 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/delay.h>
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#include "nitrox_dev.h"
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#include "nitrox_csr.h"
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/**
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* emu_enable_cores - Enable EMU cluster cores.
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* @ndev: N5 device
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*/
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static void emu_enable_cores(struct nitrox_device *ndev)
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{
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union emu_se_enable emu_se;
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union emu_ae_enable emu_ae;
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int i;
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/* AE cores 20 per cluster */
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emu_ae.value = 0;
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emu_ae.s.enable = 0xfffff;
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/* SE cores 16 per cluster */
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emu_se.value = 0;
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emu_se.s.enable = 0xffff;
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/* enable per cluster cores */
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for (i = 0; i < NR_CLUSTERS; i++) {
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nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);
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nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);
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}
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}
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/**
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* nitrox_config_emu_unit - configure EMU unit.
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* @ndev: N5 device
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*/
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void nitrox_config_emu_unit(struct nitrox_device *ndev)
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{
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union emu_wd_int_ena_w1s emu_wd_int;
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union emu_ge_int_ena_w1s emu_ge_int;
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u64 offset;
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int i;
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/* enable cores */
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emu_enable_cores(ndev);
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/* enable general error and watch dog interrupts */
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emu_ge_int.value = 0;
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emu_ge_int.s.se_ge = 0xffff;
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emu_ge_int.s.ae_ge = 0xfffff;
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emu_wd_int.value = 0;
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emu_wd_int.s.se_wd = 1;
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for (i = 0; i < NR_CLUSTERS; i++) {
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offset = EMU_WD_INT_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, emu_wd_int.value);
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offset = EMU_GE_INT_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, emu_ge_int.value);
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}
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}
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static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
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{
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union nps_pkt_in_instr_ctl pkt_in_ctl;
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union nps_pkt_in_instr_baoff_dbell pkt_in_dbell;
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union nps_pkt_in_done_cnts pkt_in_cnts;
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u64 offset;
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offset = NPS_PKT_IN_INSTR_CTLX(ring);
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/* disable the ring */
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_in_ctl.s.enb = 0;
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nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
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usleep_range(100, 150);
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/* wait to clear [ENB] */
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do {
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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} while (pkt_in_ctl.s.enb);
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/* clear off door bell counts */
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offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(ring);
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pkt_in_dbell.value = 0;
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pkt_in_dbell.s.dbell = 0xffffffff;
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nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
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/* clear done counts */
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offset = NPS_PKT_IN_DONE_CNTSX(ring);
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pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
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usleep_range(50, 100);
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}
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
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{
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union nps_pkt_in_instr_ctl pkt_in_ctl;
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u64 offset;
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/* 64-byte instruction size */
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offset = NPS_PKT_IN_INSTR_CTLX(ring);
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_in_ctl.s.is64b = 1;
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pkt_in_ctl.s.enb = 1;
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nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
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/* wait for set [ENB] */
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do {
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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} while (!pkt_in_ctl.s.enb);
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}
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/**
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* nitrox_config_pkt_input_rings - configure Packet Input Rings
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* @ndev: N5 device
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*/
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void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
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{
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int i;
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for (i = 0; i < ndev->nr_queues; i++) {
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struct nitrox_cmdq *cmdq = &ndev->pkt_cmdqs[i];
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union nps_pkt_in_instr_rsize pkt_in_rsize;
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u64 offset;
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reset_pkt_input_ring(ndev, i);
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/* configure ring base address 16-byte aligned,
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* size and interrupt threshold.
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*/
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offset = NPS_PKT_IN_INSTR_BADDRX(i);
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nitrox_write_csr(ndev, NPS_PKT_IN_INSTR_BADDRX(i), cmdq->dma);
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/* configure ring size */
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offset = NPS_PKT_IN_INSTR_RSIZEX(i);
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pkt_in_rsize.value = 0;
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pkt_in_rsize.s.rsize = ndev->qlen;
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nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
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/* set high threshold for pkt input ring interrupts */
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offset = NPS_PKT_IN_INT_LEVELSX(i);
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nitrox_write_csr(ndev, offset, 0xffffffff);
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enable_pkt_input_ring(ndev, i);
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}
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}
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static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_ctl pkt_slc_ctl;
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union nps_pkt_slc_cnts pkt_slc_cnts;
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u64 offset;
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/* disable slc port */
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offset = NPS_PKT_SLC_CTLX(port);
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_slc_ctl.s.enb = 0;
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nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
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usleep_range(100, 150);
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/* wait to clear [ENB] */
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do {
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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} while (pkt_slc_ctl.s.enb);
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/* clear slc counters */
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offset = NPS_PKT_SLC_CNTSX(port);
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pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
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usleep_range(50, 100);
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}
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_ctl pkt_slc_ctl;
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u64 offset;
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offset = NPS_PKT_SLC_CTLX(port);
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pkt_slc_ctl.value = 0;
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pkt_slc_ctl.s.enb = 1;
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/*
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* 8 trailing 0x00 bytes will be added
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* to the end of the outgoing packet.
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*/
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pkt_slc_ctl.s.z = 1;
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/* enable response header */
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pkt_slc_ctl.s.rh = 1;
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nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
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/* wait to set [ENB] */
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do {
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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} while (!pkt_slc_ctl.s.enb);
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}
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static void config_single_pkt_solicit_port(struct nitrox_device *ndev,
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int port)
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{
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union nps_pkt_slc_int_levels pkt_slc_int;
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u64 offset;
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reset_pkt_solicit_port(ndev, port);
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offset = NPS_PKT_SLC_INT_LEVELSX(port);
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pkt_slc_int.value = 0;
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/* time interrupt threshold */
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pkt_slc_int.s.timet = 0x3fffff;
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nitrox_write_csr(ndev, offset, pkt_slc_int.value);
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enable_pkt_solicit_port(ndev, port);
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}
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void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
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{
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int i;
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for (i = 0; i < ndev->nr_queues; i++)
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config_single_pkt_solicit_port(ndev, i);
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}
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/**
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* enable_nps_interrupts - enable NPS interrutps
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* @ndev: N5 device.
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*
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* This includes NPS core, packet in and slc interrupts.
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*/
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static void enable_nps_interrupts(struct nitrox_device *ndev)
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{
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union nps_core_int_ena_w1s core_int;
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/* NPS core interrutps */
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core_int.value = 0;
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core_int.s.host_wr_err = 1;
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core_int.s.host_wr_timeout = 1;
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core_int.s.exec_wr_timeout = 1;
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core_int.s.npco_dma_malform = 1;
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core_int.s.host_nps_wr_err = 1;
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nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
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/* NPS packet in ring interrupts */
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
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/* NPS packet slc port interrupts */
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
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}
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void nitrox_config_nps_unit(struct nitrox_device *ndev)
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{
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union nps_core_gbl_vfcfg core_gbl_vfcfg;
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/* endian control information */
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nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);
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/* disable ILK interface */
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core_gbl_vfcfg.value = 0;
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core_gbl_vfcfg.s.ilk_disable = 1;
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core_gbl_vfcfg.s.cfg = PF_MODE;
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nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
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/* config input and solicit ports */
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nitrox_config_pkt_input_rings(ndev);
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nitrox_config_pkt_solicit_ports(ndev);
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/* enable interrupts */
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enable_nps_interrupts(ndev);
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}
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void nitrox_config_pom_unit(struct nitrox_device *ndev)
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{
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union pom_int_ena_w1s pom_int;
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int i;
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/* enable pom interrupts */
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pom_int.value = 0;
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pom_int.s.illegal_dport = 1;
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nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);
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/* enable perf counters */
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for (i = 0; i < ndev->hw.se_cores; i++)
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nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
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}
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/**
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* nitrox_config_rand_unit - enable N5 random number unit
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* @ndev: N5 device
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*/
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void nitrox_config_rand_unit(struct nitrox_device *ndev)
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{
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union efl_rnm_ctl_status efl_rnm_ctl;
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u64 offset;
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offset = EFL_RNM_CTL_STATUS;
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efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
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efl_rnm_ctl.s.ent_en = 1;
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efl_rnm_ctl.s.rng_en = 1;
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nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
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}
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void nitrox_config_efl_unit(struct nitrox_device *ndev)
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{
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int i;
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for (i = 0; i < NR_CLUSTERS; i++) {
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union efl_core_int_ena_w1s efl_core_int;
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u64 offset;
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/* EFL core interrupts */
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offset = EFL_CORE_INT_ENA_W1SX(i);
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efl_core_int.value = 0;
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efl_core_int.s.len_ovr = 1;
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efl_core_int.s.d_left = 1;
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efl_core_int.s.epci_decode_err = 1;
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nitrox_write_csr(ndev, offset, efl_core_int.value);
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offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, (~0ULL));
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offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i);
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nitrox_write_csr(ndev, offset, (~0ULL));
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}
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}
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void nitrox_config_bmi_unit(struct nitrox_device *ndev)
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{
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union bmi_ctl bmi_ctl;
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union bmi_int_ena_w1s bmi_int_ena;
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u64 offset;
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/* no threshold limits for PCIe */
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offset = BMI_CTL;
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bmi_ctl.value = nitrox_read_csr(ndev, offset);
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bmi_ctl.s.max_pkt_len = 0xff;
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bmi_ctl.s.nps_free_thrsh = 0xff;
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bmi_ctl.s.nps_hdrq_thrsh = 0x7a;
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nitrox_write_csr(ndev, offset, bmi_ctl.value);
|
||
|
|
|
||
|
|
/* enable interrupts */
|
||
|
|
offset = BMI_INT_ENA_W1S;
|
||
|
|
bmi_int_ena.value = 0;
|
||
|
|
bmi_int_ena.s.max_len_err_nps = 1;
|
||
|
|
bmi_int_ena.s.pkt_rcv_err_nps = 1;
|
||
|
|
bmi_int_ena.s.fpf_undrrn = 1;
|
||
|
|
nitrox_write_csr(ndev, offset, bmi_int_ena.value);
|
||
|
|
}
|
||
|
|
|
||
|
|
void nitrox_config_bmo_unit(struct nitrox_device *ndev)
|
||
|
|
{
|
||
|
|
union bmo_ctl2 bmo_ctl2;
|
||
|
|
u64 offset;
|
||
|
|
|
||
|
|
/* no threshold limits for PCIe */
|
||
|
|
offset = BMO_CTL2;
|
||
|
|
bmo_ctl2.value = nitrox_read_csr(ndev, offset);
|
||
|
|
bmo_ctl2.s.nps_slc_buf_thrsh = 0xff;
|
||
|
|
nitrox_write_csr(ndev, offset, bmo_ctl2.value);
|
||
|
|
}
|
||
|
|
|
||
|
|
void invalidate_lbc(struct nitrox_device *ndev)
|
||
|
|
{
|
||
|
|
union lbc_inval_ctl lbc_ctl;
|
||
|
|
union lbc_inval_status lbc_stat;
|
||
|
|
u64 offset;
|
||
|
|
|
||
|
|
/* invalidate LBC */
|
||
|
|
offset = LBC_INVAL_CTL;
|
||
|
|
lbc_ctl.value = nitrox_read_csr(ndev, offset);
|
||
|
|
lbc_ctl.s.cam_inval_start = 1;
|
||
|
|
nitrox_write_csr(ndev, offset, lbc_ctl.value);
|
||
|
|
|
||
|
|
offset = LBC_INVAL_STATUS;
|
||
|
|
|
||
|
|
do {
|
||
|
|
lbc_stat.value = nitrox_read_csr(ndev, offset);
|
||
|
|
} while (!lbc_stat.s.done);
|
||
|
|
}
|
||
|
|
|
||
|
|
void nitrox_config_lbc_unit(struct nitrox_device *ndev)
|
||
|
|
{
|
||
|
|
union lbc_int_ena_w1s lbc_int_ena;
|
||
|
|
u64 offset;
|
||
|
|
|
||
|
|
invalidate_lbc(ndev);
|
||
|
|
|
||
|
|
/* enable interrupts */
|
||
|
|
offset = LBC_INT_ENA_W1S;
|
||
|
|
lbc_int_ena.value = 0;
|
||
|
|
lbc_int_ena.s.dma_rd_err = 1;
|
||
|
|
lbc_int_ena.s.over_fetch_err = 1;
|
||
|
|
lbc_int_ena.s.cam_inval_abort = 1;
|
||
|
|
lbc_int_ena.s.cam_hard_err = 1;
|
||
|
|
nitrox_write_csr(ndev, offset, lbc_int_ena.value);
|
||
|
|
|
||
|
|
offset = LBC_PLM_VF1_64_INT_ENA_W1S;
|
||
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
||
|
|
offset = LBC_PLM_VF65_128_INT_ENA_W1S;
|
||
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
||
|
|
|
||
|
|
offset = LBC_ELM_VF1_64_INT_ENA_W1S;
|
||
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
||
|
|
offset = LBC_ELM_VF65_128_INT_ENA_W1S;
|
||
|
|
nitrox_write_csr(ndev, offset, (~0ULL));
|
||
|
|
}
|