100 lines
3.0 KiB
Plaintext
100 lines
3.0 KiB
Plaintext
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Qualcomm adreno/snapdragon hdmi output
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Required properties:
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- compatible: one of the following
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* "qcom,hdmi-tx-8996"
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* "qcom,hdmi-tx-8994"
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* "qcom,hdmi-tx-8084"
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* "qcom,hdmi-tx-8974"
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* "qcom,hdmi-tx-8660"
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* "qcom,hdmi-tx-8960"
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- reg: Physical base address and length of the controller's registers
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- reg-names: "core_physical"
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- interrupts: The interrupt signal from the hdmi block.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See ../clocks/clock-bindings.txt for details.
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- core-vdda-supply: phandle to supply regulator
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- hdmi-mux-supply: phandle to mux regulator
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- phys: the phandle for the HDMI PHY device
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- phy-names: the name of the corresponding PHY device
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Optional properties:
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- hpd-gpios: hpd pin
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- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
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- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
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- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
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- power-domains: reference to the power domain(s), if available.
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- pinctrl-names: the pin control state names; should contain "default"
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- pinctrl-0: the default pinctrl state (active)
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- pinctrl-1: the "sleep" pinctrl state
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HDMI PHY:
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Required properties:
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- compatible: Could be the following
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* "qcom,hdmi-phy-8660"
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* "qcom,hdmi-phy-8960"
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* "qcom,hdmi-phy-8974"
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* "qcom,hdmi-phy-8084"
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* "qcom,hdmi-phy-8996"
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- #phy-cells: Number of cells in a PHY specifier; Should be 0.
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- reg: Physical base address and length of the registers of the PHY sub blocks.
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- reg-names: The names of register regions. The following regions are required:
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* "hdmi_phy"
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* "hdmi_pll"
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For HDMI PHY on msm8996, these additional register regions are required:
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* "hdmi_tx_l0"
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* "hdmi_tx_l1"
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* "hdmi_tx_l3"
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* "hdmi_tx_l4"
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- core-vdda-supply: phandle to vdda regulator device node
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Example:
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/ {
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...
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hdmi: hdmi@4a00000 {
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compatible = "qcom,hdmi-tx-8960";
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reg-names = "core_physical";
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reg = <0x04a00000 0x2f0>;
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interrupts = <GIC_SPI 79 0>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names =
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"core_clk",
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"master_iface_clk",
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"slave_iface_clk";
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clocks =
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<&mmcc HDMI_APP_CLK>,
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<&mmcc HDMI_M_AHB_CLK>,
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<&mmcc HDMI_S_AHB_CLK>;
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qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
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qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
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qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
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core-vdda-supply = <&pm8921_hdmi_mvs>;
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hdmi-mux-supply = <&ext_3p3v>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
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pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi_phy";
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};
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hdmi_phy: phy@4a00400 {
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compatible = "qcom,hdmi-phy-8960";
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reg-names = "hdmi_phy",
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"hdmi_pll";
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reg = <0x4a00400 0x60>,
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<0x4a00500 0x100>;
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#phy-cells = <0>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names = "slave_iface_clk";
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clocks = <&mmcc HDMI_S_AHB_CLK>;
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core-vdda-supply = <&pm8921_hdmi_mvs>;
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};
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};
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