57 lines
2.2 KiB
Plaintext
57 lines
2.2 KiB
Plaintext
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Some socs have a large number of interrupts requests to service
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the needs of its many peripherals and subsystems. All of the
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interrupt lines from the subsystems are not needed at the same
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time, so they have to be muxed to the irq-controller appropriately.
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In such places a interrupt controllers are preceded by an CROSSBAR
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that provides flexibility in muxing the device requests to the controller
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inputs.
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Required properties:
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- compatible : Should be "ti,irq-crossbar"
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- reg: Base address and the size of the crossbar registers.
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- interrupt-controller: indicates that this block is an interrupt controller.
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- interrupt-parent: the interrupt controller this block is connected to.
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- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
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- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
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- ti,reg-size: Size of a individual register in bytes. Every individual
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register is assumed to be of same size. Valid sizes are 1, 2, 4.
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- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
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crossbar. These interrupt lines are reserved in the soc,
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so crossbar bar driver should not consider them as free
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lines.
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Optional properties:
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- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
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SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
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crossbar. These irqs have a crossbar register, but still cannot be used.
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- ti,irqs-safe-map: integer which maps to a safe configuration to use
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when the interrupt controller irq is unused (when not provided, default is 0)
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Examples:
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crossbar_mpu: crossbar@4a002a48 {
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compatible = "ti,irq-crossbar";
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reg = <0x4a002a48 0x130>;
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ti,max-irqs = <160>;
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ti,max-crossbar-sources = <400>;
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ti,reg-size = <2>;
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ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
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ti,irqs-skip = <10 133 139 140>;
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};
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Consumer:
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========
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See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
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Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
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further details.
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An interrupt consumer on an SoC using crossbar will use:
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interrupts = <GIC_SPI request_number interrupt_level>
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Example:
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device_x@0x4a023000 {
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/* Crossbar 8 used */
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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...
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};
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